//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
#ifndef _GPIO_H_
#define _GPIO_H_


/* Begin of GPIO Pin Values  */
#define GPIO_P_PMU_IRQ                0
#define GPIO_P_EJACK_RECO             1
#define GPIO_P_SYS_EN                 2
#define GPIO_P_PWR_SCL                3
#define GPIO_P_PWR_SDA                4
#define GPIO_PWR_CAP0                 5
#define GPIO_PWR_CAP1                 6
#define GPIO_PWR_CAP2                 7
#define GPIO_PWR_CAP3                 8
#define GPIO_P_AC97_13M               9
#define GPIO_P_BB_32K                 10
#define GPIO_EMPTY0                   11
#define GPIO_P_CIF_DD7                12
#define GPIO_P_SPI_TXD                13
#define GPIO_P_SPI_FRM                14
#define GPIO_P_FASTSLEEP              15
#define GPIO_P_LCD_BLCTL              16
#define GPIO_P_CIF_DD6                17
#define GPIO_EMPTY1                   18
#define GPIO_P_BT_WAKE                19
#define GPIO_P_DOC_IRQ                20
#define GPIO_EMPTY2                   21
#define GPIO_P_BB_FLASH               22
#define GPIO_P_BB_RESETN              23
#define GPIO_P_LCD_nRESET             24
#define GPIO_P_ONKEY_N                25
#define GPIO_RTS0                     26
#define GPIO_CTS0                     27
#define GPIO_P_AC97_BITCLK            28
#define GPIO_P_AC97_SDIN              29
#define GPIO_P_AC97_SDOUT             30
#define GPIO_P_AC97_SYNC              31
#define GPIO_P_SDIO_CLK               32
#define GPIO_EMPTY3                   33
#define GPIO_TXD0                     34
#define GPIO_P_SDIO_CD                35
#define GPIO_P_SPI_SCLK               36
#define GPIO_RXD0                     37
#define GPIO_P_BB_HOST_WAKEUP         38
#define GPIO_EMPTY4                   39
#define GPIO_P_USB_FULL_SPEED         40
#define GPIO_P_USB_OTG_ID             41
#define GPIO_P_BT_TXD                 42
#define GPIO_P_BT_RXD                 43
#define GPIO_P_BT_RTS                 44
#define GPIO_P_BT_CTS                 45
#define GPIO_P_RXD0                   46
#define GPIO_P_TXD0                   47
#define GPIO_P_CIF_DD5                48
#define GPIO_EMPTY5                   49
#define GPIO_P_CIF_DD3                50
#define GPIO_P_CIF_DD2                51
#define GPIO_P_AUDIO_PWREN            52
#define GPIO_P_CIF_MCLK               53
#define GPIO_P_CIF_PCLK               54
#define GPIO_P_CIF_DD1                55
#define GPIO_P_CIF_PWRDN              56
#define GPIO_P_CIF_nRESET             57
#define GPIO_P_L_DD0                  58
#define GPIO_P_L_DD1                  59
#define GPIO_P_L_DD2                  60
#define GPIO_P_L_DD3                  61
#define GPIO_P_L_DD4                  62
#define GPIO_P_L_DD5                  63
#define GPIO_P_L_DD6                  64
#define GPIO_P_L_DD7                  65
#define GPIO_P_L_DD8                  66
#define GPIO_P_L_DD9                  67
#define GPIO_P_L_DD10                 68
#define GPIO_P_L_DD11                 69
#define GPIO_P_L_DD12                 70
#define GPIO_P_L_DD13                 71
#define GPIO_P_L_DD14                 72
#define GPIO_P_L_DD15                 73
#define GPIO_P_LFCLK_RD               74
#define GPIO_P_LLCLK_A0               75
#define GPIO_P_LPCLK_WR               76
#define GPIO_P_LCD_BIAS               77
#define GPIO_BTOSC_EN                 78
#define GPIO_P_SDIO_PWREN             79
#define GPIO_EMPTY6                   80
#define GPIO_P_CIF_DD0                81
#define GPIO_P_BT_PWREN               82
#define GPIO_P_CIF_DD4                83
#define GPIO_P_CIF_FV                 84
#define GPIO_P_CIF_LV                 85
#define GPIO_EMPTY7                   86
#define GPIO_EMPTY8                   87
#define GPIO_P_PA_SHUTDN              88
#define GPIO_P_VIB_PWREN              89
#define GPIO_P_HOST_WAKE              90
#define GPIO_EMPTY9                   91
#define GPIO_P_SDIO_DAT0              92
#define GPIO_EMPTY10                  93
#define GPIO_EMPTY11                  94
#define GPIO_EMPTY12                  95
#define GPIO_P_KP_MKOUT6              96
#define GPIO_P_KP_MKIN3               97
#define GPIO_P_KP_MKIN4               98
#define GPIO_P_KP_MKIN5               99
#define GPIO_P_KP_MKIN0               100
#define GPIO_P_KP_MKIN1               101
#define GPIO_P_KP_MKIN2               102
#define GPIO_P_KP_MKOUT0              103
#define GPIO_P_KP_MKOUT1              104
#define GPIO_P_KP_MKOUT2              105
#define GPIO_EMPTY13                  106
#define GPIO_P_USB_DEC_N              107
#define GPIO_P_KP_MKOUT5              108
#define GPIO_P_SDIO_DAT1              109
#define GPIO_P_SDIO_DAT2              110
#define GPIO_P_SDIO_DAT3              111
#define GPIO_P_SDIO_CMD               112
#define GPIO_P_AC97_nRST              113
#define GPIO_P_MODEM_WAKEUP           114
#define GPIO_BT_RST_N                 115
#define GPIO_P_AC97_INT               116
#define GPIO_P_I2C_SCL                117
#define GPIO_P_I2C_SDA                118
#define GPIO_EMPTY14                  119
#define GPIO_EMPTY15                  120
/* End of GPIO Pin Values  */

/**
  GPIO Register Definitions
**/
typedef struct
{
    unsigned long GPLR0;             /* Level Detect Reg. Bank 0 */
    unsigned long GPLR1;             /* Level Detect Reg. Bank 1 */
    unsigned long GPLR2;             /* Level Detect Reg. Bank 2 */
    unsigned long GPDR0;            /* Data Direction Reg. Bank 0 */
    unsigned long GPDR1;            /* Data Direction Reg. Bank 1 */
    unsigned long GPDR2;            /* Data Direction Reg. Bank 2 */
    unsigned long GPSR0;            /* Pin Output Set Reg. Bank 0 */
    unsigned long GPSR1;            /* Pin Output Set Reg. Bank 1 */
    unsigned long GPSR2;            /* Pin Output Set Reg. Bank 2 */
    unsigned long GPCR0;            /* Pin Output Clr Reg. Bank 0 */
    unsigned long GPCR1;            /* Pin Output Clr Reg. Bank 1 */
    unsigned long GPCR2;            /* Pin Output Clr Reg. Bank 2 */
    unsigned long GRER0;   /* Ris. Edge Detect Enable Reg. Bank 0 */
    unsigned long GRER1;   /* Ris. Edge Detect Enable Reg. Bank 1 */
    unsigned long GRER2;   /* Ris. Edge Detect Enable Reg. Bank 2 */
    unsigned long GFER0;   /* Fal. Edge Detect Enable Reg. Bank 0 */
    unsigned long GFER1;   /* Fal. Edge Detect Enable Reg. Bank 1 */
    unsigned long GFER2;   /* Fal. Edge Detect Enable Reg. Bank 2 */
    unsigned long GEDR0;       /* Edge Detect Status Reg. Bank 0 */
    unsigned long GEDR1;       /* Edge Detect Status Reg. Bank 1 */
    unsigned long GEDR2;       /* Edge Detect Status Reg. Bank 2 */
    unsigned long GAFR0_L;  /* Alt. Function Select Reg.[  0:15 ] */
    unsigned long GAFR0_U;  /* Alt. Function Select Reg.[ 16:31 ] */
    unsigned long GAFR1_L;  /* Alt. Function Select Reg.[ 32:47 ] */
    unsigned long GAFR1_U;  /* Alt. Function Select Reg.[ 48:63 ] */
    unsigned long GAFR2_L;  /* Alt. Function Select Reg.[ 64:79 ] */
    unsigned long GAFR2_U;  /* Alt. Function Select Reg.[ 80:95 ] */
    unsigned long GAFR3_L;  /* Alt. Function Select Reg.[ 96:111] */
    unsigned long GAFR3_U;  /* Alt. Function Select Reg.[112:120] */
    unsigned long  RESERVED1[35];    /* addr. offset 0x074-0x0fc */
    unsigned long GPLR3;             /* Level Detect Reg. Bank 3 */
    unsigned long  RESERVED2[2];      /* addr. offset 0x104-0x108 */
    unsigned long GPDR3;            /* Data Direction Reg. Bank 3 */
    unsigned long  RESERVED3[2];      /* addr. offset 0x110-0x114 */
    unsigned long GPSR3;            /* Pin Output Set Reg. Bank 3 */
    unsigned long  RESERVED4[2];      /* addr. offset 0x11c-0x120 */
    unsigned long GPCR3;            /* Pin Output Clr Reg. Bank 3 */
    unsigned long  RESERVED5[2];      /* addr. offset 0x128-0x12c */
    unsigned long GRER3;   /* Ris. Edge Detect Enable Reg. Bank 3 */
    unsigned long  RESERVED6[2];      /* addr. offset 0x134-0x138 */
    unsigned long GFER3;   /* Fal. Edge Detect Enable Reg. Bank 3 */
    unsigned long  RESERVED7[2];      /* addr. offset 0x140-0x144 */
    unsigned long GEDR3;       /* Edge Detect Status Reg. Bank 3 */
} GPIO_REGS, *PGPIO_REGS;

#endif
